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philips semiconductors FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver product specification 1999 apr 15 integrated circuits ic23 data handbook
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 2 1999 apr 15 853-2156 21253 features ? 8-bit transceivers ? latched, registered or straight through in either a to b or b to a path ? drives heavily loaded backplanes with equivalent load impedances down to 10 w . ? high drive 100ma btl open collector drivers on b-port ? allows incident wave switching in heavily loaded backplane buses ? reduced btl voltage swing produces less noise and reduces power consumption ? built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity ? compatible with ieee futurebus+ or proprietary btl backplanes ? each btl driver has a dedicated bus gnd for a signal return ? controlled output ramp and multiple gnd pins minimize ground bounce ? glitch-free power up/power down operation ? low i cc current ? tight output skew ? supports live insertion ? pins for the optional jtag boundary scan function are provided ? high density packaging in plastic quad flatpack ? 5v compatible i/o on a-port quick reference data symbol parameter typical unit t plh t phl propagation delay ain to bn 3.0 3.0 ns t plh t phl propagation delay bn to aon 5.0 5.3 ns c ob output capacitance (b0 bn only) 6 pf i ol output current (b0 bn only) 100 ma i cc suppl y current ain to bn outputs low outputs high 9 14 ma i cc su ly current bn to aon (outputs low) 17 ma bn to aon (outputs high) 14 ordering information package commercial range v cc = 3.3v 10%; t amb = 40 c to +85 c dwg no. 52-pin plastic quad flat pack (pqfp) FBL2033bb sot379-1 note: thermal mounting or forced air is recommended pin configuration oeb0 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 bus gnd b1 bus gnd b2 bus gnd b3 bus gnd b4 bus gnd b5 bus gnd b6 bus gnd logic gnd ao1 ao2 ao3 loopback ai4 ai 5 ao6 ao7 b7 ai1 ao0 oea lcba bias v b0 lgoic gnd lcab 8-bit universal transceiver FBL2033 52-lead pqfp bg gnd oeb1 logic gnd v cc ai2 ai3 ao4 ai 6 logic gnd ai7 sab0 sab1 v cc bus gnd v cc ao 5 ai0 sba1 sba0 bg v cc sg00088
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 3 description the FBL2033 is an 8-bit transceiver featuring a split input (ai) and output (ao) bus on the ttl-level side. the common i/o, open collector b port operates at btl signal levels. the logic element for data flow in each direction is controlled by two pairs of mode select inputs (sba0 and sba1 for b-to-a, sab0 and sab1 for a-to-b). it can be configured as a buffer, a register, or a d-type latch. when configured in the buffer mode, the inverse of the input data appears at the output port. in the flip-flop mode, data is stored on the rising edge of the appropriate clock input (lcab or lcba). in the latch mode, clock pins serve as transparent-high latch enables. regardless of the mode, data is inverted from input to output. data flow in the b-to-a direction, regardless of the logic element selected, is further controlled by the loopback input. when the loopback input is high the output of the selected a-to-b logic element (not inverted) becomes the b-to-a input. the 3-state ao port is enabled by asserting a high level on oea. the b port has two output enables, oeb0 and oeb1 . only when oeb0 is high and oeb1 is low is the output enabled. when either oeb0 is low or oeb1 is high, the b-port is inactive and is pulled to the level of the pull-up voltage. new data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-state (ao port) or inactive (b port). the b-port drivers are low-capacitance open collectors with controlled ramp and are designed to sink 100ma. precision band gap references on the b-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55v. the b-port interfaces to abackplane transceiver logico (see the ieee 1194.1 btl standard). btl features low power consumption by reducing voltage swing (1v p-p, between 1v and 2v) and reduced capacitive loading by placing an internal series diode on the drivers. btl also provides incident wave switching, a necessity for high performance backplanes. output clamps are provided on the btl outputs to further reduce switching noise. the av oh o clamp reduces inductive ringing effects during a low-to-high transition. the av oh o clamp is always active. the other clamp, the atrapped reflectiono clamp, clamps out ringing below the btl 0.5v v ol level. this clamp remains active for approximately 100ns after a high-to-low transition. to support live insertion, oeb0 is held low during power on/off cycles to ensure glitch- free b port drivers. proper bias for b port drivers during live insertion is provided by the bias v pin when at a 3.3v level while v cc is low. the bias v pin is a low current input which will reverse-bias the btl driver series schottky diode, and also bias the b port output pins to a voltage between 1.62v and 2.1v. this bias function is in accordance with ieee btl standard 1194.1. if live insertion is not a requirement, the bias v pin should be tied to a v cc pin. the logic gnd and bus gnd pins are isolated inside the package to minimize noise coupling between the btl and ttl sides. these pins should be tied to a common ground external to the package. each btl driver has an associated bus gnd pin that acts as a signal return path and these bus gnd pins are internally isolated from each other. in the event of a ground return fault, a ahardo signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot. as with any high power device thermal considerations are critical. it is recommended that airflow (300ifpm) and/or thermal mounting be used to ensure proper junction temperature. pin description symbol pin number type name and function ai0 ai7 50, 52, 3, 5, 8, 10, 12, 15 input data inputs (ttl) ao0 ao7 51, 2, 4, 6, 9, 11, 14, 16 output 3-state outputs (ttl) b0 b7 40, 38, 36, 34, 32, 30, 28, 26 i/o data inputs/open collector outputs, high current drive (btl) oeb0 23 input enables the b outputs when high oeb1 24 input enables the b outputs when low oea 43 input enables the ao outputs when high bus gnd 39, 37, 35, 33, 31, 29, 27, 25 gnd bus ground (0v) logic gnd 1, 13, 17, 49 gnd logic ground (0v) v cc 18, 22, 48 power positive supply voltage bias v 41 power live insertion pre-bias pin bg v cc 44 power band gap threshold voltage reference bg gnd 42 gnd band gap threshold voltage reference ground sabn 20, 21 input mode select from ai to b sban 45, 46 input mode select from b to ao lcab 47 input a-to-b clock/latch enable (transparent latch when high) lcba 19 input b-to-a clock/latch enable (transparent latch when high) loopback 7 input enables loopback function when high (from ain to aon)
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 4 function table inputs outputs mode ain bn * oeb0 oeb1 oea lcab lcba sab 1 0 sba 1 0 aon bn ain to bn thru mode l e h l l x x ll xx z h** ain to bn thr u mode h e h l l x x ll xx z l ain to bn trans p arent latch l e h l l h x hx xx z h** ain to bn transparent latch h e h l l h x hx xx z l ain to bn latch and read l e h l l x hx xx z h** ain to bn latch and read h e h l l x hx xx z l ain to bn register l e h l l x lh xx z h** ain to bn register h e h l l x lh xx z l bn outputs latched and read (preconditioned latch) x e h l l l x hx xx z latched data bn to aon thru mode x l l h h x x xx ll h input bn to aon thr u mode x h l h h x x xx ll l input bn to aon trans p arent latch x l l h h x h xx hx h input bn to aon transparent latch x h l h h x h xx hx l input bn to aon latch and read x l l h h x xx hx h input bn to aon latch and read x h l h h x xx hx l input bn to aon register x l l h h x xx lh h input bn to aon register x h l h h x xx lh l input aon outputs latched and read (preconditioned latch) x x l h h x l xx hx latched data x disable bn out p uts x x l x x x x xx xx x h** disable bn o u tp u ts x x x h x x x xx xx x h** disable aon outputs x x x x l x x xx xx z x function select table mode selected sxx1 sxx0 thru mode l l register mode l h latch mode h x notes: h = high voltage level l = low voltage level h = high voltage level one set-up time prior to the high-to-low lcxx transition l = low voltage level one set-up time prior to the high-to-low lcxx transition x = don't care z = high-impedance (off) state e = input not externally driven = low-to-high transition = high-to-low transition h** = goes to level of pull-up voltage bn * = precaution should be taken to ensure b inputs do not float. if they do, they are equal to low state. in loopback mode (loopback = high), ain inputs are routed to the aon outputs. the bn inputs are blocked out.
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 5 logic diagram 23 24 oeb0 oeb1 20 sab0 21 sab1 47 lcab d en d clk 50 ain 40 bn 1 of 8 cells 19 45 46 43 d en d clk 51 lcba sba0 sba1 oea aon 1 of 8 cells 42 bggnd bgref 52, 2, 5, 8, 10, 12, 15 2, 4, 6, 9, 11, 14, 16 38, 36, 34, 32, 30, 28, 26 7 loopback sg00069 absolute maximum ratings operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted these lim its are over the operating free-air temperature range. symbol parameter rating unit v cc supply voltage -0.5 to +4.6 v v in in p ut voltage ai0 ai7, oeb0, oebn , oean -0.5 to +7.0 v v in in ut voltage b0 b7 -0.5 to +3.5 i in input current v in 0 -50 v out voltage applied to output in high output state -0.5 to +7.0 v i out current applied to output in ao0 ao7 64, 64 ma i out low output state/high output state b0 b7 200 ma t stg storage temperature -65 to +150 c
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 6 recommended operating conditions symbol parameter commercial limits v cc = 3.3v 10%; t amb = 40 to +85 c unit min typ max v cc supply voltage 3.0 3.3 3.6 v v ih high-level in p ut voltage except b0 b7 2.0 v v ih high - level in ut voltage b0 b7 1.62 1.55 v il low-level in p ut voltage except b0 b7 0.8 v v il low - level in ut voltage b0 b7 1.47 i ik input clamp current -18 ma i oh high-level output current ao0 ao7 -12 ma i ol low-level out p ut current ao0 ao7 +12 ma i ol low - level out ut current b0 b7 100 c ob output capacitance on b port 6 7 pf t amb operating free-air temperature range 0 +70 c live insertion specifications symbol parameter limits unit symbol parameter min typ max unit v biasv bias pin voltage voltage difference between the bias voltage and v cc after the pcb is plugged in. 0.5 v i s bias pin (i bia s v ) input v cc = 0 v, bias v = 3.6v 1.2 ma i biasv ( biasv ) dc current v cc = 3.3v, bias v = 3.6v 10 m a v bn bus voltage during prebias b0 b7 = 0v, bias v = 3.3v 1.62 2.1 v i lm fall current during prebias b0 b7 = 2v, bias v = 1.3 to 2.5v 1 m a i hm rise current during prebias b0 b7 = 1v, bias v = 3 to 3.6v -1 m a i bn peak peak bus current during insertion v cc = 0 to 3.3v, b0 b7 = 0 to 2.0v, bias v = 2.7 to 3.6v, oeb0 = 0.8v, t r = 2ns 10 ma i o off power u p current v cc = 0 to 3.3v, oeb0 = 0.8v 100 m a i ol off po w er u p c u rrent v cc = 0 to 1.2v, oeb0 = 0 to 5v 100 m a t gr input glitch rejection v cc = 3.3v 1.0 1.35 ns
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 7 dc electrical characteristics over recommended operating free-air temperature range unless otherwise noted. symbol p arameter test conditions 1 limits unit s y mbol parameter test conditions 1 min typ 2 max u nit i oh high level output current b0 b7 v cc = max, v il = max, v oh = 1.9v 100 m a i o power off out p ut current b0 b7 v cc = 0v, v il = max, v oh = 1.9v 100 m a i off po w er - off o u tp u t c u rrent b0 b7 v cc = 0v, v il = max, v oh = 1.9v@85 c 300 m a v high - level out p ut ao0 ao7 3 v cc = min to max; i oh = -100 m a v cc 0.2 v v oh high level out ut voltage ao0 ao7 3 v cc = min; i oh = -8ma 2.4 v v cc = min; i oh = -32ma 2.0 v ao0 ao7 3 v cc = min; i ol = 16ma 0.4 v v ol low-level output voltage ao0 ao7 3 v cc = min; i ol = 32ma 0.5 v b0 b7 v cc = min, i ol = 4ma 0.5 v v cc = min, i ol = 100ma 0.75 1.0 1.20 v v ik input clamp voltage v cc = min, i i = i ik = 18ma 0.85 -1.2 v control pins v cc = 3.6v; v i = v cc or 300mv 1.0 i i input leakage current control/ ai0 ai7 v cc = 0v or 3.6v; v i = 5.5v 10 m a i g ai0 ai7 v cc = 3.6v; v i = v cc 1 m note 4 v cc = 3.6v; v i = 300mv 5 v cc = max v =19v 100 m a v cc = max , v i = 1 . 9v 100 m a i ih high-level input current b0 b7 v cc = max, v i = 3.5v, note 5 100 ma v cc = max, v i = 3.75v, note 5 @ 40 c 100 ma i low level in p ut current b0 b7 v = max v = 0 75v 100 m a i il lo w- le v el inp u t c u rrent b0 b7 v cc = max , v i = 0 . 75v - 100 m a i ozh off-state output current ao0 ao7 v cc = max, v o =3v 5 m a i ozl off-state output current ao0 ao7 v cc = max, v o = 0.5v -5 m a i cch su pp ly current (total) v cc = max, outputs high 14 31 ma cch i ccl su ly current (total) b a v cc = max, outputs low 17 38 ma i ccz supply current v cc = max 22 55 ma i cch su pp ly current (total) v cc = max, outputs high 14 32 ma cch i ccl su ly current (total) a b v cc = max, outputs low 9 18 ma i ccz supply current v cc = max 14 33 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operation conditions for the applic able type. 2. all typical values are at v cc = 3.3v, t a = 25 c. 3. due to test equipment limitations, actual test conditions are v ih = 1.8v and v il = 1.3v for the b side. 4. unused pins are at v cc or gnd. 5. for b port input voltage between 3 and 5 volt; i ih will be greater than 100ma but the part will continue to function normally (clamping circuit is active).
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 8 ac electrical characteristics industrial and commercial (a to b) symbol parameter test condition min typ max min max unit t plh t phl propagation delay, an to b n through latch 1.2 1.2 2.7 2.6 4.8 4.3 1.0 1.0 5.3 4.9 ns t plh t phl propagation delay, an to b n transparent latch 1.3 1.8 3.2 3.7 5.2 5.6 1.0 1.6 6.1 6.3 ns t plh t phl propagation delay, lcab to b n latch 2.0 2.3 3.8 4.3 5.8 6.3 1.2 1.8 7.0 7.3 ns t plh t phl propagation delay, lcab to b n register 2.1 2.0 3.8 4.3 5.7 6.5 1.4 1.8 6.9 7.3 ns t plh t phl propagation delay, sabx to b n inverting 1.2 2.3 4.3 5.1 7.6 8.0 1.0 2.0 9.2 8.7 ns t plh t phl propagation delay, sabx to b n non-inverting 1.8 1.8 4.0 5.0 6.4 8.5 1.1 1.6 8.0 9.8 ns t plh t phl oebn to b n 1.5 1.6 3.4 3.4 5.4 5.3 1.0 1.0 6.0 7.2 ns ac electrical characteristics industrial and commercial (a to b) symbol parameter test condition t amb = +25 c, v cc = 3.3v, r l = 16.5 w t amb = 40 to +85 c, v cc = 3.3v 10%, r l = 16.5 w unit min typ max min max t plh t phl propagation delay, an to b n through latch 1.2 1.2 2.8 2.4 4.5 4.0 1.0 1.0 5.7 4.6 ns t plh t phl propagation delay, an to b n transparent latch 1.4 1.7 3.2 3.5 5.1 5.4 1.0 1.3 6.1 5.9 ns t plh t phl propagation delay, lcab to b n latch 2.0 2.2 3.8 4.1 5.6 6.1 1.3 1.6 6.9 7.0 ns t plh t phl propagation delay, lcab to b n register 2.0 2.2 3.9 4.1 5.9 6.1 1.2 1.6 7.7 7.0 ns t plh t phl propagation delay, sabx to b n inverting 1.2 1.8 4.6 4.7 8.6 7.9 1.0 1.6 10.4 8.7 ns t plh t phl propagation delay, sabx to b n non-inverting 1.3 1.5 4.5 4.6 8.2 8.2 1.0 1.2 10.0 9.1 ns t plh t phl oebn to b n 1.5 1.5 3.4 3.2 6.0 7.2 1.0 1.0 6.3 7.0 ns
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 9 ac electrical characteristics industrial and commercial (b to a) symbol parameter test condition t amb = +25 c, v cc = 3.3v t amb = 40 to +85 c, v cc = 3.3v 10% unit symbol parameter test condition min typ max min max unit t plh t phl propagation delay, b n to an through mode 2.5 3.0 4.5 5.1 6.5 7.3 1.6 2.6 7.8 9.1 ns t plh t phl propagation delay, b n to an transparent latch 3.4 3.2 5.4 5.4 7.6 7.6 2.2 2.7 9.2 9.3 ns t plh t phl propagation delay, lcab to an latch 2.1 1.6 3.9 3.3 5.8 5.0 1.3 1.2 7.2 5.9 ns t plh t phl propagation delay, lcab to an register 1.9 2.3 3.7 4.1 5.7 6.0 1.1 1.8 6.8 7.0 ns t plh t phl propagation delay, sabx to an inverting 2.3 2.5 4.2 4.5 6.4 6.5 1.3 2.0 7.9 7.4 ns t plh t phl propagation delay, sabx to an non-inverting 1.4 1.9 3.9 4.0 8.7 6.1 1.0 1.5 9.8 7.1 ns t plh t phl propagation delay, ain to aon loopback 2.4 2.3 4.3 4.4 6.3 6.6 1.6 1.6 8.1 7.6 ns t plh t phl propagation delay, lpbk to an non-inverting or inverting 2.0 1.3 4.3 4.9 7.0 9.4 1.4 1.5 8.9 11.3 ns t pzh t phz propagation delay, oea to an 2.4 3.1 4.3 5.3 6.3 7.6 1.9 2.5 7.3 8.9 ns t pzh t phz propagation delay, oea to an 2.1 1.4 4.0 2.7 6.2 4.4 1.7 1.0 6.9 5.2 ns
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 10 ac setup requirements industrial and commercial limits symbol parameter test condition t amb = +25 c, v cc = 3.3v t amb = 40 to +85 c, v cc = 3.3v 10% unit condition c l = 50pf (a side) / c d = 30pf (b side) r l = 500 w (a side) / r u = 9 w (b side) min min t s (h) t s (l) setup time ain to lcab or bn to lcba 3.0 3.0 4.0 4.0 ns t h (h) t h (l) hold time (latch mode) ain to lcab 6.0 5.0 6.5 5.5 ns t h (h) t h (l) hold time (register mode) ain to lcab 1.0 1.0 1.3 1.3 ns t h (h) t h (l) hold time (latch mode) b n to lcab 1.5 1.5 2.0 2.0 ns t h (h) t h (l) hold time (register mode) b n to lcab 1.0 1.0 1.3 1.3 ns t w (h) t w (l) pulse width, high or low ain to lcab or b n to lcba 3.0 3.0 4.0 4.0 ns ac setup requirements industrial and commercial limits symbol parameter test condition t amb = +25 c, v cc = 3.3v t amb = 40 to +85 c, v cc = 3.3v 10% unit condition c l = 50pf (a side) / c d = 30pf (b side) r l = 500 w (a side) / r u = 16.5 w (b side) min min t s (h) t s (l) setup time ain to lcab or bn to lcba 3.0 3.0 4.0 4.0 ns t h (h) t h (l) hold time (latch mode) ain to lcab 6.0 5.0 6.5 5.5 ns t h (h) t h (l) hold time (register mode) ain to lcab 1.0 1.0 1.3 1.3 ns t h (h) t h (l) hold time (latch mode) b n to lcab 1.5 1.5 2.0 2.0 ns t h (h) t h (l) hold time (register mode) b n to lcab 1.0 1.0 1.3 1.3 ns t w (h) t w (l) pulse width, high or low ain to lcab or b n to lcba 3.0 3.0 4.0 4.0 ns
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 11 ac waveforms v m t s t pzl input output v m v m v m v m t plh t phl v m v m v m v m t phl t plh output ain, bn aon, bn v m v m t sk (o) aon oea v m v m t plz v m v ol +0.3v aon oea v m v m v m v oh -0.3v ov t phz t pzh input ain, bn lcab, lcba v m v m 1/f max t h t s t h t w (l) t w (h) note: the shaded areas indicate when the input is permitted to change for predictable output performance. waveform 1. propagation delay for data or output enable to output waveform 2. propagation delay for data or output enable to output waveform 3. output to output skew waveform 4. setup and hold times, pulse widths and maximum frequency waveform 5. 3-state output enable time to high level and output disable time from high level waveform 6. 3-state output enable time to low level and output disable time from low level sg00070
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver 1999 apr 15 12 test circuit and waveforms 2.5ns 2.0ns 500ns 500ns input pulse requirements rep. rate amplitude t tlh t thl 1mhz 3.0v 2.5ns input pulse definitions v m = 1.55v for bn , v m = 1.5v for all others. v cc family fb+ d.u.t. pulse generator 7.0v r l r l c l r t v in v out test circuit for 3-state outputs on a port test switch switch position t plz, t pzl all other closed open definitions: r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. c d = load capacitance includes jig and probe capacitance; see ac characteristics for value. r u = pull up resistor; see ac characteristics for value. t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse amp (v) low v low v t thl (t f ) t tlh (t r ) t w t w low v 0.0v t tlh (t r ) t thl (t f ) amp (v) a port 1mhz 2.0v 2.0ns 1.0v b port v cc d.u.t. pulse generator r u c d r t v in v out test circuit for outputs on b port bias v 2.0v (for r u = 9 w ) 2.1v (for r u = 16.5 w ) sg00063
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru futurebus+ universal interface transceiver 1999 apr 15 13 qfp52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm sot379-1
philips semiconductors product specification FBL2033 3.3v btl 8-bit latched/registered/pass-thru universal transceiver yyyy mmm dd 14 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 07-98 document order number: 9397-75005517
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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